This invention relates in general to multiplexer circuits, and more particularly, to a high speed CMOS multiplexer circuit having reduced propagation delay in the data path and selected path.
A multiplexing circuit is a common and useful component of many modern digital systems wherein there is a need to select between one of a plurality of input signals under control of a digital select signal. For example, in a four-to-one digital multiplexer, four digital input signals are applied at four data inputs while 2-bit digital select signal is applied at the select inputs thereof. The four possible combinations of the 2-bit digital select signal propagates the inverse state of the selected digital input signal to the output terminal. Other multiplexing circuits can accommodate a greater number of input signals with additional select bits. For example, an eight-to-one multiplexer requires a 3-bit digital select signal and a sixteen-to-one multiplexer uses a 4-bit digital select signal.
The conventional multiplexing circuit comprises a parallel combination of processing channels, one for each input signal, coupled between a positive source of operating potential such as V.sub.CC and a ground potential terminal. Each processing channel typically includes at least six serially couple CMOS transistors, three upper P-channel CMOS transistors, and three lower N-channel CMOS transistors. The drain of the lower P-channel CMOS transistor and the drain of the highest N-channel CMOS transistor in each conduction channel are coupled together to the output node. The gates of the CMOS transistors are coupled for receiving the digital select signals and input signals such that the digital select signal enables four of the six serially coupled transistors in one conduction path while the data input signal enables one of the remaining two transistors whereby either the three upper P-channel CMOS transistors or the three lower N-channel CMOS transistors are conducting. The output terminal is thus pulled toward V.sub.CC or ground potential through the three upper transistors or the three lower transistors depending on the digital input signal for providing the inverse state thereof.
The aforedescribed conventional multiplexer circuit includes a propagation delay through the six transistor conduction paths wherein the positive supply V.sub.CC or ground potential must pass through the three upper P-channel CMOS transistors or the three lower N-channel CMOS transistors, respectively, to reach the output terminal. The drain-to-source resistance and the ever present junction capacitance of each transistor creates an undesirable RC time constant for the propagating signal. Hence, the greater the number of transistors in a conduction path, the greater resistance and capacitance and associated propagation delay therethrough. Thus, it would be desirable to reduce the number of transistors in the data conduction path for each processing channel of the multiplexer.
Another concern in achieving reduced propagation delay through the multiplexer circuit is the parasitic drain capacitances associated with the P.sup.+ diffusion to N.sup.- bulk junction of the P-channel CMOS transistors and the N.sup.+ diffusion to P.sup.- bulk junction of the N-channel CMOS transistors. Theses junction capacitances are affixed to the output terminal at the junction of the lowest P-channel CMOS transistor and the highest N-channel CMOS transistor. Depending on the state of the digital input signals, it is common for the P-channel CMOS and N-channel CMOS transistors on either side of the output terminal in the non-selected processing channels to be conducting thereby adding the parasitic junction capacitances of the P-channel and N-channel CMOS transistors next in line in the conduction paths which serves to further load the output terminal slowing the charge and discharge rate thereof and increasing the propagation delay through the multiplexer circuit.
Previous attempts at speeding up the multiplexer circuit have included increasing size of the CMOS transistors for increasing the drive capacity thereof. This technique is often ineffective since the increase in size of the CMOS transistors also increases the parasitic drain capacitance of each transistor connected to the output terminal of which only one is attempting to drive the capacitive load. To maintain symmetry it is necessary to increase the size of all the CMOS transistors equally effectively increasing the parasitic drain capacitance by a factor of four and defeating the attempt at higher speed by driving the capacitive loads harder. A more desirable approach would be to reduce the capacitive load on the output terminal rather than drive it with additional power.
Hence, what is needed is an improved CMOS multiplexing circuit having fewer transistors in the conduction paths of each processing channel while reducing the capacitive load on the output terminal.